BelaSigna 300 ON Semiconductor
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Optimized open platform for design flexibility

BelaSigna 300's CFX/HEAR dual-core architecture has unmatched flexibility with a 24-bit open-programmable DSP core and a highly configurable accelerator signal processing engine. BelaSigna 300 delivers the flexibility of a generic DSP with the power consumption and size of a fixed-function ASIC.

The dual-core architecture facilitates an evenly balanced workload, optimizing processing efficiency and minimizing processor clock speed and power consumption.

HEAR Configurable Accelerator Engine

The highly flexible accelerator engine operates in parallel with the CFX to efficiently perform common signal processing tasks, including low-delay, high-fidelity analysis and synthesis filterbanks in uniform or non-uniform bands.

CFX DSP Core

The fully programmable 24-bit dual-MAC digital signal processor (DSP) core is optimized to master the BelaSigna 300 system as it simultaneously runs advanced, computationally intensive algorithms such as echo cancellation, adaptive noise reduction and speech enhancement.

Inputs

BelaSigna 300's four independent audio inputs allow for more advanced audio processing algorithms to be deployed in applications such as hands-free car kits. The four input sources can be used simultaneously for multiple microphones or direct analog audio inputs. Multiple interfaces give the flexibility to seamlessly connect to other systems and typical HMI devices.

SoC Single Die 130nm

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