Mitigation Strategies
Changing the lead plating material to 100% matte Sn (tin) from SnPb raises industry concerns about tin whisker growth. ON Semiconductor has implemented the following mitigation strategies to minimize the occurrence of tin whiskers.
- Increased the plating thickness from 5 µ m to 7.5 µ m minimum; 10 um nominal.
- Implemented a post - plate anneal of 150 ° C for 1 hour within 24 hours of plating
- Implemented strict plating process controls
Whisker Testing
ON Semiconductor has conducted tin whisker testing following the guidelines of JEDEC standard JESD22A121. Testing has been conducted on packages utilizing Alloy 42 and Cu leadframe materials with matte tin lead finish. Three test conditions have been used to evaluate whisker growth: Temperature Cycling (-55/+85°C) Ambient Storage at 30°C/60%RH, and High Temperature/High Humidity Storage at 60°C/87%RH.
ON Semiconductor’s whisker acceptance specification meets JEDEC JESD-201 for Class 2 Type of Products, 45 microns maximum for Temperature Cycle and 40 microns maximum for Temperature & Humidity tests. All whisker test results to date have passed these specifications.
Baseline tin whisker test results available for ON Semiconductor assembly sites. Click on each report to download.
Tin Whisker report for ON Semiconductor site in Leshan using matte tin plating over Alloy42 leadframe
Tin Whisker report for ON Semiconductor site in Seremban using matte tin plating over Alloy42 leadframe
Tin Whisker report for ON Semiconductor site in Seremban using matte tin plating over Copper leadframe
Tin Whisker report for ON Semiconductor site in Carmona using matte tin plating over Copper leadframe
Tin Whisker Application Note |
